It is known that, in general, when the resolution of a Digital to Analog Converter, DAC, is increased, i.e. the number of digital bits that it accepts in a digital input word increases, the space on a circuit, such as an integrated circuit, to implement the DAC also increases. Each extra bit can effectively double the size of a DAC.
Prior art attempts to reduce the size of DACs have involved “segmentation”. Segmentation in the context of a Digital-to-Analog Converter (DAC) means dividing the digital input word of the DAC into several sub-words. The sub-words serve as the inputs for several segments of the DAC which can be regarded as sub-DAC's whose outputs are combined to generate the overall analog output of the DAC. This technique allows the component count and hence area consumed by the DAC components for a given resolution to be reduced and it is widely used for DACs whose resolution is beyond 10 bits. However, applying segmentation to a DAC produces side-effects which can negatively impact the performance of the resulting segmented DAC. Notably:
1) When the original DAC is inherently monotonic (the slope of the transfer function does not present a sign change for any input), which is a desirable feature, applying segmentation may involve losing the inherent monotonicity;
2) The dynamics of the resulting segmented DAC can be significantly worse than those associated with the original DAC, especially in terms of a transition glitch. It is desirable that transitions from one DAC code to another DAC code do not introduce too severe a glitch (both in terms of magnitude and duration) as this can adversely affect subsequent circuitry. The desirability of avoiding glitches during code transitions has generally limited attempts to provide segmented DACs to two levels of segmentation. In practice segmentation beyond two levels is generally perceived to exacerbate transition glitches, especially for transitions between segments. This has been an obstacle to working with more than two levels of segmentation.
Monotonic behavior (i.e. an increase in the digital input word always results in an increase in the analog output or more strictly the transfer function is entirely non-increasing or entirely non-decreasing, as appropriate, so for a sequence of increasing digital codes the output value should not have regions where it decreases interposed with regions where it increases) in a DAC is an important feature of operation.